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ADVANCE INFORMATION
DRX 3960A Digital Receiver Front-end
Edition Feb. 8, 2001 6251-510-2AI
MICRONAS
DRX 3960A
Contents Page 4 4 5 6 7 7 7 7 8 8 8 8 8 8 8 8 8 9 9 9 10 10 10 11 11 11 12 13 14 14 14 14 14 15 15 15 16 18 19 19 19 21 22 23 Section 1. 1.1. 1.2. 1.3. 1.3.1. 1.3.2. 1.3.3. 1.3.4. 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 2.7. 2.8. 3. 3.1. 3.2. 3.3. 3.4. 3.5. 4. 4.1. 4.1.1. 4.1.2. 4.1.3. 4.1.4. 4.1.4.1. 4.1.4.2. 4.1.4.3. 4.2. 4.3. 4.4. 4.4.1. 4.4.2. 4.4.3. 5. 5.1. 5.2. 5.3. 5.4. 5.5. Title Introduction Features Quick Reference Data Analog TV Application Initialization for Analog TV Multistandard Configuration for B/G, L, I, D/K and M/N Multistandard Configuration for L' FM Radio Functional Description Input Amplifier with TOP Setting Carrier Recovery Channel Filtering and Audio/Video Splitting Video and Tuner AGC Group Delay Equalizing Peaking SIF AGC Output Ports Standard Specific Filter Curves Standard B Standard G Standard D/K, I, L/L' Standard M/N Standard FM Control Interface I2C Bus Interface Device and Subaddresses Description of CONTROL Register Protocol Description Proposals for General DRX 3960A I2C Telegrams Symbols Write Telegrams Read Telegrams List of Control Registers List of Status Registers Description of User Registers Write Register on I2C Subaddress 03hex Write Register on I2C Subaddress 10hex Read Register on I2C Subaddress 11hex Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Pin Configuration Electrical Characteristics
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DRX 3960A
Contents, continued Page 23 23 24 24 24 28 30 Section 5.5.1. 5.5.2. 5.5.3. 5.5.4. 5.6. 6. 7. Title Absolute Maximum Ratings Recommended Operating Conditions Recommended Crystal Characteristics Recommended Tuner Characteristics Characteristics Application Circuit Data Sheet History
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DRX 3960A
Digital Receiver Front-end Release Note: Revision bars indicate significant changes to the previous edition. 1. Introduction The Digital Receiver Front-end DRX 3960A performs the entire multistandard Quasi Split Sound (QSS) TV IF processing, AGC, video demodulation, and generation of the second sound IF (SIF) with only one SAW filter. The IC is designed for applications in TV sets, VCRs, PC cards, and TV tuners. The alignment-free DRX 3960A needs no special external components. All control functions and status registers are accessible via I2C bus interface. Therefore, it simplifies the design of high-quality, highly standardized IF stages. Due to its mixed signal structure and the digital demodulation, the IC offers unique features and is prepared for digital TV.
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- Standard specific digital picture carrier recovery: * alignment-free * quartz-stable and accurate * stable frequency lock at 100% modulation and overmodulation up to 150% * quartz-accurate AFC information - Programmable standard specific digital group delay equalizing - Automatically frequency-adjusted Nyquist slope, therefore optimal picture and sound performance over complete lock in frequency range - Standard-specific digital AGC and delayed tuner AGC with programmable tuner Take Over Point - Fast AGC due to linear structure - Adaptive back porch control, therefore fast positive modulation AGC - No sound traps needed at video output - Second SIF output with standard dependent pre-filtering and amplitude controlled output level - Optimal sound SNR due to carrier recovery without quadrature distortions - FM radio capability without external components and with standard TV tuner - Prepared for digital TV (DVB-C, DVB-T, ATSC) - I2C bus interface
1.1. Features - Multistandard QSS IF processing with a single SAW - Highly reduced amount of external components (no tank circuit, no potentiometers, no SAW switching) - Programmable IF frequency (38.9 MHz, 45.75 MHz, 32.9 MHz, 36.125 MHz etc.) - Digital IF processing for the following standards: B/G, D/K, I, L/L', and M/N - Standard specific digital post filtering - Standard specific digital video/audio splitting
fref
DSP
Clock Generation TAGC
D A
EQU
Tuner AGC
Carrier Recovery
IF In
TOP
A D
Filtering
VAGC
D A D A
CVBS
AAGC
2nd SIF
I2C
Fig. 1-1: Block diagram of the DRX 3960A
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DRX 3960A
1.2. Quick Reference Data
Parameter Supply voltage, analog Current consumption, analog Supply voltage, digital Current consumption, digital Input frequency Maximum wanted signal input voltage minimum TOP gain: maximum TOP gain: Lock in range 0.8 1.0 65 56 49 58 51 62/58 55/50 2 0.8 8 30 200 20 Min. Typ. 5 110 3.3 60 47 Max. Unit V mA V mA MHz mVpp mVpp MHz MHz dB dB dB dB dB Vpp Vpp V dev. = 27 kHz dev. = 27 kHz programmable programmable direction adjacent channel direction own channel center freq. quartz stable blue picture, PSC1=-13dB, no sound shelf Remarks
Intermodulation ratio 1.07 Weighted video S/N (CCIR567, 10 kHz...5 MHz) Unweighted video S/N (10 kHz...5 MHz) Weighted sound S/N (black, CCIR468 quasi peak, SC1/SC2) Weighted sound S/N (FuBK, CCIR468 quasi peak, SC1/SC2) CVBS output voltage Second IF output voltage Delayed Tuner AGC external voltage
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1.3. Analog TV Application The Digital Receiver Front-end DRX 3960A is able to replace a conventional IF IC including several SAWs. Nevertheless, quasi split sound processing is performed with standard specific internal filtering and group delay equalizing. The input signal of the DRX 3960A is the TV IF with its carrier at: - 38.9 MHz (B/G, D/K, I, L, and M/N in multistandard applications) - 32.9 MHz (L') - 45.75 MHz (M/N in single standard applications) - other frequencies are also programmable - 36.125 MHz (DVB-C or DVB-T in further versions) These signals are available from conventional tuners. For pre-filtering, one 8-MHz channel SAW filter must be used, e.g. the Epcos X6966M. Nevertheless, the entire multistandard processing is performed. The prefilter limits the signal bandwidth to 8 MHz and suppresses major parts of the adjacent channels.
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After the desired standard information is transferred into the DRX 3960A, the following standard specific procedures are performed: - Adjacent channel suppression - Carrier locking including AFC information generation - Nyquist slope adjustment - Video/sound splitting - Video AGC, including delayed tuner AGC - Group delay post distortion - Video and sound frequency shaping - Video demodulation - Second SIF generation and AGC Similar to conventional analog front-ends, the tuner gain is controlled by the DRX 3960A. New AGC algorithms have been implemented for superior level tracking for both positive and negative video modulation. The demodulated CVBS signal and the second sound IF (SIF) are available as analog output signals. If an FM radio channel is transferred to the IF inputs, down-mixed by means of a standard TV tuner, it can be preselected and further down-mixed by the DRX 3960A. Thus, a succeeding sound demodulator, e.g. the MSP, will be able to demodulate that channel. The DRX 3960A operates with its own quartz or with appropriate external clocks, e.g.: - 13.5, 20.25, 27 MHz from an employed video IC - 1, 4 MHz from the tuner
CVBS
VPC/VCT
Tuner
SAW
DRX 3960A 2nd SIF
Delayed Tuner AGC
MSP
I2C Fig. 1-2: Multistandard video and sound IF processing with DRX 3960A
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DRX 3960A
1.3.1. Initialization for Analog TV The DRX 3960A is able to operate with different reference frequencies. If 20.25 MHz is used, REF_SW has to be connected to ground; additionally, if a lower frequency is used, SYN_REF (control register) has to be set accordingly. If a higher frequency is used, REF_SW has to be connected to VDVDD and SYN_REF has to be set accordingly. In the 20.25 MHz case, no I2C command is needed. The standard which should be processed has to be set via I2C bus. Additional controlling is only needed if the default values for the remaining write registers are not applicable.
1.3.2. Multistandard Configuration for B/G, L, I, D/K and M/N In multistandard applications for B/G, L, I, D/K, and M/N, the picture carrier frequency at the tuner output should be 38.9 MHz. The sound carrier frequencies are below in a distance corresponding to the transmission standard. Thus, all wanted channel components are within the passband of the SAW and forwarded to the DRX 3960A. The demodulated and filtered video signal will be available at the CVBS output and the downconverted sound carriers will be available at the 2nd SIF output.
1.3.3. Multistandard Configuration for L' In the L standard, the band 1 channels (40 MHz to 65 MHz) have a different frequency configuration. Their sound carriers are below the according picture carrier. This sub-standard is called L'. In that case, the picture carrier frequency at the tuner output should be 32.9 MHz. Using conventional tuners, the sound carrier frequencies in L' at the tuner output are above the picture carrier. Thus, again all wanted channel components are within the passband of the SAW.
1.3.4. FM Radio In FM radio applications, the tuner has to down-convert the wanted channel to 32.4 MHz. Therefore, the lower slope of the SAW frequency response rejects adjacent carriers on one side of that channel. The DRX 3960A further down-converts the wanted channel to 5.5 MHz. After additional filtering, the signal is fed to the 2nd SIF output.
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2. Functional Description 2.1. Input Amplifier with TOP Setting The first block of the DRX 3960A is a low-noise preamplifier. It has a setable gain between 0 and 20 dB for setting the Tuner take Over Point voltage (TOP). This adjustment is responsible for optimal tuner operation. Note: The TOP is the tuner input voltage at which the IF circuit (e.g. the DRX 3960A) begins to reduce the tuner gain. Thus, above this voltage the tuner output voltage remains nearly constant. Of course, the gain of the tuner is only allowed to be reduced if the S/N is sufficiently high. A level of 60...70 dBV at the antenna input is a typical value for the starting point of gain reduction.
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is higher than 38% of the CVBS amplitude, or lower than 17%, it is set to the according limit. If the video AGC gain is to low, the tuner AGC increases its output current. Thus, the tuner reduces its gain. The actual gain value of both control loops can be read out (VID_GAIN, TAGC_I) as information about the input signal strength.
2.5. Group Delay Equalizing The group delay is set to compensate the pre-distortion of the transmitter. Additionally, the standard settings can be changed by means of four coefficients to optimize the complete signal path (EQU_0, EQU_1, EQU_2, EQU_3).
2.2. Carrier Recovery A digital PLL performs the tracking of the picture carrier and therefore synchronous demodulation. The lock in range refers to the desired IF frequency which is chosen according to the programmed TV standard (e.g. 32.9 MHz at L' or 38.9 MHz at all other standards). The PLL incorporates its own AFC function and provides the frequency offset from the desired IF frequency for external use (CR_FREQ). A special digital validation algorithm allows long frequency lock at 100% modulation. Additionally, the PLL aligns the digital calculated Nyquist slope to the picture carrier frequency. Due to its digital implementation, the carrier recovery is absolutely offset-free, alignment-free, drift-free, and quartz-accurate. 2.6. Peaking To shape the frequency response, a peaking filter is implemented. The following figure indicates the possible frequency responses:
Video Response [dB]
10 7.5 5 2.5 0 -2.5 -5 -7.5 1 2 3 4 5
Frequency [MHz]
2.3. Channel Filtering and Audio/Video Splitting According to the selected standard, channel filtering (suppression of not wanted signals) is performed internally by digital filters. These filters additionally separate the video and sound components of the desired channel and transfer them to the according output. The processing is competitive to conventional QSS systems.
Fig. 2-1: Peaking filter frequency response The peaking value is setable via I2C (VID_PEAK).
2.7. SIF AGC The SIF AGC controls the level of the sound carrier output. Four different reference amplitude values are available (SIF_REF) . The actual gain (SIF_GAIN) can be read out and set via I2C. According to the standard, the time constant is switched to FM/NICAM (fast AGC) or AM (slow AGC).
2.4. Video and Tuner AGC The video AGC controls the CVBS amplitude to a given value (VID_AMP). This value may be set via I2C bus. In positive modulation mode, an adaptive back porch control (BPC) is activated. If the detected BP reference
2.8. Output Ports Six general purpose output ports can be switched to high or low level. Micronas
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DRX 3960A
3. Standard Specific Filter Curves The external SAW only performes a coarse attenuation of major parts of adjacent channels. The main filtering is done by means of the DSP. The following figures indicate the overall filter curves of the DRX 3960A including the SAW.
3.1. Standard B Video Response [dB]
10 0 -10 -20 -30 -40 -50 -60 2 4 6 8 10
3.2. Standard G Video Response [dB]
10 0 -10 -20 -30 -40 -50 -60 2 4 6 8 10
Frequency [MHz]
Frequency [MHz]
SIF Response [dB]
10 0 -10 -20 -30 -40 -50 -60 2 4 6 8 10
SIF Response [dB]
10 0 -10 -20 -30 -40 -50 -60 2 4 6 8 10
Frequency [MHz]
Frequency [MHz]
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3.3. Standard D/K, I, L/L' Video Response [dB]
10 0 -10 -20 -30 -40 -50 -60 2 4 6 8 10
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3.4. Standard M/N Video Response [dB]
10 0 -10 -20 -30 -40 -50 -60 2 4 6 8 10
Frequency [MHz] SIF Response [dB]
10 0 -10 -20 -30 -40 -50 -60 2 4 6 8 10
Frequency [MHz] SIF Response [dB]
10 0 -10 -20 -30 -40 -50 -60 2 4 6 8 10
Frequency [MHz]
Frequency [MHz]
3.5. Standard FM SIF Response [dB]
10 0 -10 -20 -30 -40 -50 -60 2 4 6 8 10
Frequency [MHz]
10
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DRX 3960A
4. Control Interface 4.1. I2C Bus Interface 4.1.1. Device and Subaddresses The DRX 3960A is controlled via the I2C bus slave interface. The IC is selected by transmitting one of the DRX 3960A device addresses. In order to allow up to three ICs to be connected to a single bus, an address select pin (ADR_SEL) has been implemented. With ADR_SEL pulled to high, low, or left open, the DRX 3960A responds to different device addresses. A device address pair is defined as a write address and a read address. Writing is done by sending the device write address, followed by the subaddress byte, two address bytes, and two data bytes. Reading is done by sending the write device address, followed by the subaddress byte and two address bytes. Without sending a stop condition, reading of the addressed data is completed by sending the device read address and reading two bytes of data. Due to the internal architecture of the DRX 3960A, the IC cannot react immediately to an I2C request. The typical response time is about 0.3 ms. If the DRX 3960A cannot accept another complete byte of data until it has performed some other function (for example, servicing an internal interrupt), it will hold the clock line low to force the transmitter into a wait state. The maximum wait period during normal operation mode is less than 1 ms.
Table 4-1: I2C Bus Device Addresses
ADR_SEL Mode Device address Write 82hex Low Read 83hex Write 86hex High Read 87hex Write 8Ahex Left Open Read 8Bhex
Table 4-2: I2C Bus Subaddresses
Name CONTROL PORT WR_DRX RD_DRX Binary Value 0000 0000 0000 0011 0001 0000 0001 0001 Hex Value 00 03 10 11 Mode Read/Write Write Write Write Function Write Read : Software reset of DRX : Hardware error status of DRX
output port address write address read address
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4.1.2. Description of CONTROL Register
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Table 4-3: CONTROL as a Write Register
Name CONTROL Subaddress 00hex Bit[15] (MSB) 1 : RESET 0 : normal Bits[14:0] 0
Table 4-4: CONTROL as a Read Register
Name CONTROL Subaddress 00hex Bit[15] (MSB) Reset status after last reading of CONTROL: 0 : no reset occurred 1 : reset occurred Bit>@ Internal hardware status: 0 : no error occurred 1 : internal error occurred BitV>@ not of interest
Reading of CONTROL will reset the bits[15,14] of CONTROL. After Power-on, bit[15] of CONTROL will be set; it must be read once to be reset.
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4.1.3. Protocol Description Write protocol
S Wait write device address ACK sub-addr ACK addr-byte ACK addr-byte ACK data-byte- ACK data-byte ACK P high low high low
Read protocol
S Wait write device address ACK sub-addr ACK addr-byte ACK addr-byte ACK S high low read device address Wait ACK data-byte- ACK data-byte NAK P high low
Write to Control or Test Registers
S Wait write device address ACK sub-addr ACK data-byte ACK data-byte ACK P high low
Write to Port Registers
S Wait write device address ACK sub-addr ACK data-byte ACK P
Note: S = P= ACK = NAK = Wait =
I2C bus Start Condition from master I2C bus Stop Condition from master Acknowledge-Bit: LOW on I2C_DA from slave (= DRX, light gray) or master (= controller dark gray) Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate `End of Read' or from DRX indicating internal error state I2C clock line is held low, while the DRX is processing the I2C command. This waiting time is max. 1 ms
I2C_DA S I2C_CL
1 0 P
Fig. 4-1: I2C bus protocol (MSB first; data must be stable while clock is high)
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4.1.4. Proposals for General DRX 3960A I2C Telegrams 4.1.4.1. Symbols daw dar < > aa dd write device address (82hex, 86hex or 8Ahex) read device address (83hex, 87hex or 8Bhex) Start Condition Stop Condition Address Byte Data Byte
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4.1.4.2. Write Telegrams write to CONTROL register write data into DRX
4.1.4.3. Read Telegrams read data from DRX
4.2. List of Control Registers
Table 4-5: List of Control Registers
Write Register Address (hex) Bits Description Reset (hex)
I2C Subaddress = 03hex ; Register is not readable. Output ports no [5:0] Output level of Ports 0
I2C Subaddress = 10hex ; Register are not readable. Standard select Level settings Reference divider 00 20 10 01 10 10 [11:0] [9:0] [8:0] Transmission standard [VID_PEAK, SIF_REF, VID_AMP] [for 4 MHz, 13 MHz, 20.25 MHz, 27 MHz or other REF_SW = high REF_SW = low] [0 dB ... 20 dB] Equalizer coefficient Equalizer coefficient Equalizer coefficient Equalizer coefficient 10D 0CA 3 025 197 0C5 12E 01 03
Tuner take over point Equalizer Coe. 0 Equalizer Coe. 1 Equalizer Coe. 2 Equalizer Coe. 3
10 12 10 70 10 71 10 72 10 73
[3:0] [9:0] [8:0] [8:0] [8:0]
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DRX 3960A
4.3. List of Status Registers
Table 4-6: List of Status Registers
Read Register Address (hex) Bits Description
I2C Subaddress = 11hex ; Register are not writable VIDEO_GAIN TAGC_I SIF_GAIN CR_FREQ 10 05 10 06 10 0A 10 0B [10:0] [11:0] [10:0] [8:1] Actual gain of the video AGC Actual tuner current Internal actual gain of the SIF AGC Frequency deviation referred to reference IF frequency
4.4. Description of User Registers 4.4.1. Write Register on I2C Subaddress 03hex Table 4-7: Write Register on I2C Subaddress 03hex I2C-Subaddress (hex) no Function Name
Output Port Level
bit[5] bit[4] bit[3] bit[2] bit[1] bit[0] Level at output port 5 Level at output port 4 Level at output port 3 Level at output port 2 Level at output port 1 Level at output port 0
PORT
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4.4.2. Write Register on I2C Subaddress 10hex Table 4-8: Write Register on I2C Subaddress 10hex I2C-Subaddress (hex) 00 20 Function
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Name
Standard select Defines TV standard which is to be processed bit[15:0] 00 00hex 00 01hex 00 02hex 01 03hex 00 03hex 00 04hex 00 09hex 01 09hex 00 0Ahex 00 40hex reserved reserved M/N B (default) G D/K L L' I FM
STANDARD_SEL
10 01
Level settings Defines the different output levels and frequency response bit[4:0]Video frequency response deviation at 5 MHz -8 -11.0 dB -7 -9.0 dB ... ... -2 -2.1 dB -1 -1.0 dB 0 0 dB 1 0.8 dB (default) 2 1.5 dB 3 2.1 dB ... ... 14 8.1 dB 15 8.3 dB bit[6:5] Reference value for SIF maximum amplitude: 0 1000 mVpp(default) 1 700 mVpp 2 500 mVpp 3 350 mVpp Reference value for video amplitude 0 2.0 V (default) 1 1.5 V 2 1.0 V 3 0.7 V VID_PEAK
SIF_REF
bit[8:7]
VID_AMP
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DRX 3960A
Table 4-8: Write Register on I2C Subaddress 10hex I2C-Subaddress (hex) 10 10 Function Name
Reference divider setting The DRX 3960A is able to operate with different reference frequencies. The reference divider has to be set to the value which divides the reference frequency to 100 kHz. To prevent malfunction after POR, the default value is set for fref = 27 MHz, if the pin REF_SW is connected to VDVDD or set for fref = 20.25 MHz, if the pin REF_SW is connected to GND. bit[8:0] External_Ref_Freq / 100 kHz 27 MHz 10Dhex 20.25 MHz CAhex 4 MHz 28hex
SYN_REF
10 12
Tuner Take Over Point (TOP) setting Defines the gain of the internal preamplifier to set the TOP bit[3:0] Gain of Preamplifier 0 0 dB 1 1.33 dB 2 2.67 dB ... 8 10 dB (default) ... 14 18.67 dB 15 20 dB
TOP_SET
10 70
Equalizer coefficient 0 bit[9:1] bit[0] Coefficient Update bit 0 1
EQU_0
do not update coefficients update coefficients EQU_1
10 71
Equalizer coefficient 1 bit[8:0] Coefficient
10 72
Equalizer coefficient 2 bit[8:0] Coefficient
EQU_2
10 73
Equalizer coefficient 3 bit[8:0] Coefficient
EQU_3
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4.4.3. Read Register on I2C Subaddress 11hex Table 4-9: Read Register on I2C Subaddress 11hex I2C-Subaddress (hex) 10 05 Function
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Name
Actual gain of video AGC bit[10:0] Video gain 0.05 dB/LSB 0dB = C8hex
VID_GAIN
10 06
Actual gain of tuner AGC bit[10:0] Tuner current 0.4 A/LSB
TAGC_I
10 0A
Actual gain of SIF AGC bit[10:0] SIF gain 0.05 dB/LSB 0dB = C8hex
SIF_GAIN
10 0B
AFC bit[8:1] bit[0] Frequency deviation10 kHz/LSB Lock bit: 1 : Carrier Recovery locked 0 : Carrier Recovery unlocked
CR_FREQ
10 0C
Lock Quality bit[10:0] < 080hex strong signal 080hex...700hex weak signal > 700hex no signal
CR_LOCK
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DRX 3960A
5. Specifications 5.1. Outline Dimensions
10 x 0.8 = 8 0.1 0.17 0.06 33 34 13.2 0.2 23 22 10 0.1 0.8 10 0.1 0.8
44 1 11 13.2 0.2
12
2.0 0.1 2.15 0.2 0.1
0.34 0.05
SPGS706000-5(P44)/1E
Fig. 5-1: 44-Pin Plastic Metric Quad Flat Pack (PMQFP44) Weight approximately 0.4 g Dimensions in mm
5.2. Pin Connections and Short Descriptions NC = not connected, leave vacant LV = if not used, leave vacant DVSS = if not used, connect to DVSS X = obligatory; connect as described in circuit diagram AHVSS = connect to AHVSS
Pin No.
Pin Name
Type
Supply Voltage
Connection
(If not used)
Short Description
1 2 3 4 5 6 7 8 9 10 11 12 13 14
AVSS_ADC AVDD_ADC ANATSTX ANATSTY AVDD_FE8 AVSS_FE8 AVSS_FE40 IFINX AVDD_FE40 IFINY AVSS_FE40 AVDD_SYN AVSS_SYN SHIELD IN IN AVDD_FE40 IN AVDD_FE40 I/O I/O AVDD_FE8 AVDD_FE8
X X GND GND X X X X X X X X X X
Analog ground for ADC Analog supply for ADC (+5 V) Test pin Test pin 2nd analog supply for the front-end 2nd analog ground for the front-end 1st analog ground for the front-end IF input 1st analog supply for the front-end (+5 V) IF input 1st analog ground for the front-end Analog supply for synthesizer (+5 V) Analog ground for synthesizer Shield GND
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DRX 3960A
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Pin No.
Pin Name
Type
Supply Voltage AVDD_DAC AVDD_DAC AVDD_DAC AVDD_DAC AVDD_DAC AVDD_DAC
Connection
(If not used)
Short Description
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
TEST0 TEST1 TEST2 CVBS REF_SW SIF AVDD_DAC AVSS_DAC TEST_EN RESETQ I2C_SDA I2C_SCL DVDD_CAP DVDD DVSS DVSS_CAP PORT0 PORT1 TUNER_AGC PORT2 PORT3 PORT4 ADR_SEL PORT5 DVDD_ADC DVSS_ADC XTAL_IN XTAL_OUT VREF SGND
IN IN IN OUT IN OUT
GND GND GND X X X X X
Test Pin Test Pin Test Pin CVBS output Reference frequency switch 2nd SIF output DAC supply (+5 V) DAC ground Test enable Reset I2C data I2C clock Digital supply capacitor Digital supply (+3.3 V) Digital ground Digital capacitor ground Digital output port Digital output port Tuner AGC current output Digital output port Digital output port Digital output port Address select Digital output port Digital supply for ADC (+3.3 V) Digital ground for ADC Crystal oscillator Crystal oscillator / external reference frequency ADC reference voltage ADC reference ground
IN IN I/O I/O
DVDD DVDD DVDD DVDD
GND X X X X X X X
OUT OUT OUT OUT OUT OUT IN OUT
DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD
LV LV X LV LV LV X LV X X
IN I/O
AVDD_ADC AVDD_ADC AVDD_ADC AVDD_ADC
X X X X
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ADVANCE INFORMATION
DRX 3960A
5.3. Pin Descriptions Pin 1, AVSS_ADC - Analog ground for ADC Pin 2, AVDD_ADC - Analog supply for ADC This pin must be connected to 5 V. Pin 3, ANATSTX - Reserved for test This pin should be connected to analog ground. Pin 4, ANATSTY - Reserved for test This pin should be connected to analog ground. Pin 5, AVDD_FE8 - Analog supply for analog frontend This pin must be connected to 5 V. Pin 6, AVSS_FE8 - Analog ground for analog frontend Pin 7, AVSS_FE40 - Analog ground for IF input circuitry. The layout of the IF input should be symmetrical with respect to AVDD_FE40. Pin 8, IFINX - Balanced IF input X This pin must be connected to SAW output. SAW has to be placed as close as possible. The layout of the IF input should be symmetrical with respect to AVDD_FE40. Pin 9, AVDD_FE40 - Analog supply for IF input circuitry This pin must be connected to 5 V. The layout of the IF input should be symmetrical with respect to AVDD_FE40. Pin 10, IFINX - Balanced IF input Y This pin must be connected to SAW output. SAW has to be placed as close as possible. The layout of the IF input should be symmetrical with respect to AVDD_FE40. Pin 11, AVSS_FE40 - Analog ground for IF input circuitry The layout of the IF input should be symmetrical with respect to AVDD_FE40. Pin 12, AVDD_SYN - Analog supply for clock synthesizer. This pin must be connected to 5 V. Pin 13, AVSS_SYN - Analog ground for clock synthesizer. Pin 14, SHIELD - Analog ground for shielding analog from digital part. Pin 15,16,17, TEST0 1 2 - Pins for factory test Pin 18, CVBS - Video output Output level is set via I2C-Bus. An appropriate video processor (e.g. VPC etc.) has to be connected to that pin. Pin 19, REF_SW- Reference frequency switch. This input defines the default setting of the reference divider after POR. For 20.25 MHz applications it has to be connected to ground, for applications with higher frequencies than 20.25 MHz it must be connected to 3.3 V. Pin 20, SIF - 2nd sound IF ouput Output level is set via I2C-Bus. An appropriate sound processor (e.g. MSP) has to be connected to that pin. Pin 21, AVDD_DAC - Analog supply for the analog output DACs This pin must be connected to 5 V. Pin 22, AVSS_DAC - Analog Ground for the analog output DACs This pin must be connected to ground. Pin 23, TEST_EN - Test Enable pin This pin enables factory test modes. For normal operation it must be connected to ground. Pin 24, RESET - Reset input For normal operation, a high level is required. A low level resets the DRX 3960A. Pin 25, 26, I2C_SDA, I2C_SCL- I2C control bus data and clock Pin 27, DVDD_CAP - Digital supply pin This pin has to be connected to 3.3 V according to the application circuit. Pin 28, DVDD - Digital supply pin This pin has to be connected to 3.3 V according to the application circuit. Pin 29, DVSS - Digital ground pin This pin has to be connected to digital ground according to the application circuit. Pin 30, DVSS_CAP - Digital ground pin This pin has to be connected according to the application circuit. Pin 31, 32, 34, 35, 36, 38, PORT0 1 2 3 4 5 - General purpose output ports Their states are controlled via I2C bus. Pin 33, TUNER_AGC - This pin controls the delayed tuner AGC. As it is a noise-shaped-I-DAC output, it has to be connected according to the application circuit.
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DRX 3960A
Pin 37, ADR_SEL - I2C Bus address select By means of this pin, one of three device addresses can be selected. Pin 39, DVDD_ADC - Digital supply pin for ADC This pin has to be connected to 3.3 V. Pin 40, DVSS_ADC - Digital ground pin for ADC. This pin has to be connected to digital ground. Pin 41, XTAL_IN - Crystal input pin If an external clock is used this pin should be left open. A crystal should be placed as close as possible to this pin. External capacitors at each crystal pin to ground are required. It should be verified by layout, that no supply current is flowing through the ground connection point. Pin 42, XTAL_OUT - Crystal output pin If an external clock is used, it has to be connected to this pin. A crystal should be placed as close as possible to this pin. External capacitors at each crystal pin to ground are required. It should be verified by layout, that no supply current is flowing through the ground connection point. Pin 43, VREF - Analog reference voltage This pin must be connected to SGND via a circuitry according to the application circuit. Pin 43, SGND - Reference for analog ground This pin must be connected separately to a single ground point.
TUNER_AGC
ADVANCE INFORMATION
5.4. Pin Configuration
DVDD DVSS DVSS_CAP PORT0 PORT1 DVDD_CAP I2C_SCL I2C_SDA RESETQ TEST_EN
33 32 31 30 29 28 27 26 25 24 23 PORT2 PORT3 PORT4 ADR_SEL PORT5 DVDD_ADC DVSS_ADC XTAL_IN XTAL_OUT VREF SGND 34 35 36 37 38 39 40 41 42 43 44 1 AVSS_ADC AVDD_ADC ANATSTX ANATSTY AVDD_FE8 AVSS_FE8 2 3 4 5 6 7 8 9 10 11 AVSS_FE40 IFINY AVDD_FE40 IFINX AVSS_FE40 22 21 20 19 18 AVSS_DAC AVDD_DAC SIF REF_SW CVBS TEST2 TEST1 TEST0 SHIELD AVSS_SYN AVDD_SYN
DRX 3960A
17 16 15 14 13 12
Fig. 5-2: 44-pin PMQFP package
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ADVANCE INFORMATION
DRX 3960A
5.5. Electrical Characteristics 5.5.1. Absolute Maximum Ratings Symbol TA PTOT TS VSUPmax Vmax Parameter Ambient Operating Temperature Maximum Power Dissipation Storage Temperature Supply Voltage, all Supply Inputs External Voltage, all VASUP Pins, (without TUNER_AGC) External Voltage, all VDSUP Pins External Voltage, I2C VSUP-tun TUNER_AGC Voltage I2C_SDA I2C_SCL TUNER_AGC Pin Name Min. 0 - -40 -0.3 -0.3 -0.3 Max. 70 833 125 6 VASUP+0.3 VDSUP+0.3 6 8 Unit
C
mW
C
V V V V V
-0.3
-
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
5.5.2. Recommended Operating Conditions Symbol VASUP Parameter Voltage, Analog Supply Pins Pin Name AVDD_ADC AVDD_FE8 AVDD_FE40 AVDD_SYN AVDD_DAC DVDD DVDD_CAP DVDD_ADC I2C_SDA I2C_SCL XTAL_IN/ OUT XTAL_IN XTAL_IN Min. 4.75 Typ. 5.0 Max. 5.25 Unit V
VDSUP VDSUP_ADC Vext_I2C fXTAL fexternal fssbnoise
Voltage, Digital Supply Pins Voltage, Digital Supply Pins, ADC External Voltage I2C Clock Frequency External Clock Frequency Range SSB-Phase noise of External Clock Frequency fratio = 20*Log10 (40.5 MHz/fexternal)
3.0 3.0 0.0 - 1
3.3 3.3 - 20.25 20.25
3.6 3.6 5.5 - 30 -90 fratio
V V V MHz MHz dBc fm = 1 kHz
The values given under "Characteristics" are valid for these "Recommended Operating Conditions".
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DRX 3960A
5.5.3. Recommended Crystal Characteristics Symbol TA fP Parameter Operating Ambient Temperature Parallel Resonance Frequency with Load Capacitance CL = 13 pF Accuracy of Adjustment Frequency Temperature Drift Series Resistance Shunt Capacitance Min. 0 - - - - 3 Typ. - 20.250000 - - - -
ADVANCE INFORMATION
Max. 70 -
Unit
C
MHz ppm ppm
fP/fP fP/fP
RR C0
100 30
25 7
pF
5.5.4. Recommended Tuner Characteristics Symbol atuner Stuner Parameter Minimum Gain Control Range AGC Control Voltage Sensitivity Min. 40 50 Typ. Max. Unit dB dB/V
5.6. Characteristics
Symbol
Supply Idig Iana Ptot Current Consumption, digital Current Consumption, analog Total Power Consumption 60 110 750 mA mA mW
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Digital Input Levels VDIGIL VDIGIH ZDIGI IDLEAK VDIGIL VDIGIH IADRSEL Digital Input Low Voltage Digital Input High Voltage Input Impedance Digital Input Leakage Current Digital Input Low Voltage Digital Input High Voltage Input Current Address Select Pin ADR_SEL 0.8 TEST_EN REF_SW 0.8 5 0.2 VDVDD VDVDD pF
-1
1 0.2
A
VDVDD VDVDD
0 V < VINPUT< VDVDD
-500
-220
220 500
A A
VADR_SEL= VDVSS VADR_SEL= VDVDD
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ADVANCE INFORMATION
DRX 3960A
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Digital Output Levels VPORTL VPORTH IPORT Reset VRHL VRLH I2C-Bus VI2CIL VI2CIH tI2C1 tI2C2 tI2C5 tI2C6 tI2C3 tI2C4 fI2C VI2COL II2COH tI2COL1 tI2COL2 IF Input Zin Differential Input Impedance R C Input Frequency IFINX, IFINY I2C-Bus Input Low Voltage I2C-Bus Input High Voltage I2C Start Condition Setup Time I2C Stop Condition Setup Time I2C-Data Setup Time before Rising Edge of Clock I2C-Data Hold Time after Falling Edge of Clock I2C-Clock Low Pulse Time I2C-Clock High Pulse Time I2C-Bus Frequency I2C-Data Output Low Voltage I2C-Data Output High Leakage Current I2C-Data Output Hold Time after Falling Edge of Clock I2C-Data Output Setup Time before Rising Edge of Clock 15 I2C_CL, I2C_DA I2C_CL I2C_CL, I2C_DA 0.6 120 120 55 0.3 VDVDD VDVDD ns ns ns Reset High Low transition Reset Low High transition RESET RESET 1.1 2.1 V V Digital Output Low Voltage Digital Output High Voltage PORT 0, 1, 2, 3, 4, 5 VDVDD 0.4 0.4 V V IPORT = 1.6 mA IPORT = -1.6 mA
Digital Output Current
-2
2
mA
55
ns
500 500 1.0 0.4 1.0
ns ns MHz V II2COL = 3 mA VI2COH = 5 V
A
ns
100
ns
fI2C = 1 MHz
1.6 1
2
2.4 4 47
k pF MHz
fin Vwanted
IFINX, IFINY IFINX, IFINY
38.9
Maximum wanted Signal Input Voltage TOP = 0 TOP = 15
FS 200 97 20 77 mVpp dBuV mVpp dBuV mV fin = 38.9 MHz, TOP gain = 10 dB
SIF
Sensitivity (S/N unweighted = 26 dB)
IFINX, IFINY
1
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DRX 3960A
ADVANCE INFORMATION
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Low Noise Preamplifier (with Tuner Take Over Point Setting) TOPmin TOPmax TOPstep Minimum Gain Maximum Gain Stepsize of Gain 0 20 1.33 dB dB dB
Analog Front-end Gtol Total Gain Tolerance
1
dB
matched inputs
Carrier Recovery DAFC flock Frequency Tolerance = AFC Accuracy Lock in range = frequency true demodulation range 0.8 1.0 50 kHz
MHz MHz
direction: adjacent channel direction: own channel
VIF AGC fVAGC BWn BWp BWpinc Control Bandwidth negative modulation positive modulation positive modulation increasing signal (white picture) positive modulation back porch control 200 1 200 Hz Hz Hz
BWbp
200
Hz
Tuner AGC, Current Output ITAGC Vsup_tun Video Output Vsync Vvidmax Sync Level (minimum DAC value) Maximum Level (maximum DAC value) CVBS 1.2 1.4 1.6 V Maximum Output Sink Current Maximum Output Voltage TUNER_ AGC 680 800 920 8
A
V
90 % FS
3.8 2.9 2.4 2.0 2.4 1.7 1.2 0.8 6
4.0 3.3 2.7 2.3 2.6 1.9 1.3 0.9
4.2 3.7 3.0 2.6 2.8 2.1 1.4 1.0
V
@ VID_AMP=0 @ VID_AMP=1 @ VID_AMP=2 @ VID_AMP=3 @ VID_AMP=0 @ VID_AMP=1 @ VID_AMP=2 @ VID_AMP=3 CLoad < 30 pF, RLoad_AC > 1 k f < 6 MHz Weighted video S/N (CCIR567, 10 kHz...5 MHz) Unweighted video S/N (10 kHz...5 MHz) blue picture, PSC1=-13dB, no sound shelf
Vvidpp
Full Scale Voltage
Vpp
f-1dBvid Routvid SNRvidw SNRvidu
Cutoff Frequency
MHz
Output Resistance Weighted Video S/N 56 58
50
dB
Unweighted Video S/N
49
51
dB
1.07
Intermodulation ratio
65
dB
1.07= PCC-P1.07 +3dB
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ADVANCE INFORMATION
DRX 3960A
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Sound IF Output Vsifpp Full Scale Voltage SIF 1.5 1.1 0.8 0.6 6 Vpp @ SIF_REF=0 @ SIF_REF=1 @ SIF_REF=2 @ SIF_REF=3 CLoad < 30 pF, RLoad_AC > 1 k f < 6 MHz black picture, CCIR 468
f-1dBsif Routsif SNRb SNRw SNRfubk
Cutoff Frequency f-1dB Output Resistance Weighted Sound S/N SC1/SC2 Weighted Sound S/N SC1/SC2 Weighted Sound S/N SC1/SC2
MHz
50 62/58
dB
62/58
dB
white picture, CCIR 468
55/50
dB
FuBK picture, CCIR 468
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6. Application Circuit
ADVANCE INFORMATION
28
REF_SW
Micronas
ADVANCE INFORMATION
DRX 3960A
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DRX 3960A
7. Data Sheet History 1. Advance Information: "DRX 3960A Digital Receiver Front-end", Aug. 10, 2000, 6251-510-1AI. First release of the advance information. 2. Advance Information: "DRX 3960A Digital Receiver Front-end", Feb. 8, 2001, 6251-510-2AI. Second release of the advance information. Major changes: - reduction of front-end gain - positive detection bit removed - output level setting changed - lock detection bit added
ADVANCE INFORMATION
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-510-2AI
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
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